Module 1 VLSI Overview

• Overview of VLSI
• VLSI Systems Evolution
• VLSI Systems Apps
• Processor-Based Systems
• Embedded Systems
• FPGA-Based Systems
• VHDL language overview
• Digital System Design with FPGAs
• Understanding Spartan-3 FPGAs

Module 2 Combinational Logic Design

• Logical functions Standard Description
• MSI circuits
• Multiplexers/Demultiplexers
• Karnaugh map method
• Adders & Subtractors
• Overview of (ALU) Arithmetic Logic Unit 
• Encoders & Decoders

Module 3 Understanding Digital Electronics

• Digital Electronics Overview
• Number systems
• Code conversions
• Concepts of Arithmetic & Boolean algebra
• Overview of Logic Gates

Module 4 Understanding Flip Flops

• Overview of Flip-flops
• Flip-flops Types
• Conversion & Application of flip flops

Module 5 Designing of Memories

• Overview of Memories
• Memory Organization & Operation
• Increasing memory size & capacity
• Memory Types

Module 6 Understand Sequential Circuit Design

• Overview of Registers & Application of Registers
• Types of shift registers
• Overview of Counters
• Synchronous & Asynchronous Counters
• Clocked sequential circuits

Module 7 Design Circuit using VHDL

• Overview of VHDL
• Code Structure & Entity
• Library Functions
• Architecture & Package Declaration
• Declaring Configuration 

Module 8 Programmable Logic Devices  

• Overview of Logic Devices
• Programmable logic array (PLAs) & Array logic (PALs)
• CPLD-Complex Programmable Logic Devices 
• Overview of FPGA-Field programmable gate array
• CAD-Computer-Aided Design Tools

Module 9 Elements of VHDL LANGUAGES

• Different Data types
• Operators
• Attributes
• Generic
• Ident

Module 10 VHDL Modelling Types

• VHDL Modelling Techniques
• Concepts of Behavioral Modelling
• Statements: If, Case, Wait, Loop, and Process

Module 11 Identiifiers

• Overview of Variables
• Signals

Module 12 Structural and Dataflow Modelling

• When & Block statements
• Statement Generation
• Component Declaration & Instantiation

Module 13 Understanding Test Bench

• Test Bench Modelling
• Use Test Bench for Combinational & Sequential Circuits

Module 14 Overview of VHDL-Verilog HDL

• CAD Evolution
• Key Design flow
• Verilog HDL Popularity
• HDL Importance
• Synthesis & Design with VHDL

Module 15 Concepts of Modelling

• Design methods
• Module Concepts & Modeling Types

Module 16 Modules

• Continuous Assignments
• Expression Operators
• Types of Operators 
• Delays

Module 17 Understanding Tasks & Functions

• Diff. B/w Function & Task
• Overview of Function & Task

Module 18 Misc Basic Concepts

• Understand Lexical Conventions
• Number Specifications
• Strings & Data Types
• Compiler Directives
• System Task
• Behavioural Modeling & Structured Processes
• Event-Base Timing Control
• Types of Statements: Initial, Always, Conditional, If, Case, and Loop
• Switch-Level Modeling